Derivation of Don't care Conditions

In this paper we present a framework for the derivation of don', care conditions by permrbaIion analysis of combinational multiple-level digital cUcuilS. The contribution of the paper is two-fold. First. different approximations of observability don', care selS are compared quantitatively. S~d. the perturbation analysis is used to derive new compatible obsa'Vabilily don', care sets. that are larger than those previously derived. 1 Introd uction Multiple-level logic optimization Sb'ategies [9, 10, 12. 4] are based on circuit b'ansfonnations that preserve the circuit behavior and improve its quality. Different flavors of circuit transfsed. Optimization algorithms based on Boolean transformations, such as those used in [9] [4] and [12], have shown to be very effective in reducing the circuit area and delay as wen as improving its testability p~es. Don't C4re conditions playa central role in the specification and optimization of logic circuits. IOOeed, they represent he degrees of freedom of transforming a network intO an equivalent one. The computation of exa:t and approximate don't care sets has been object of extensive investigation. Several algorithms have been proposed [7, 10, 13, 16, 12. IS] for the calculation of observability don't care sets by backward network IJaversal. It has been observed that the optimization of a gate changes the don't care of Other gates in die network. For this reason, the concept of compatible don't care sets has been introduced [12. IS]. The contribution of this paper is two-fold. First we review the analysis of don't care conditioos in combinational multiple-level circuits, and present a quantitative comparative analysis of approximate don't care seL Second, we analyze the problem of computing compatible and maximally compatible don't care sets, and show in particular that it is indeed possible to compute compatible don't care sets that are larger than those previously believed maximal [15"]. Basic concepts and definitions 2 We consider in this paper combinational multiple-level logic circuits. We assume that mese circuits consist of an inter<:onnection of multiple-input single-oulput combinational logic gates. Fanout points are modeled by single-input multiple-output copy gates, as shown in Fig. (1). We model these circuits by Boolean networks. A Boolean network is described by a directed acyclic graph G = (V, E). The elements of the vertex set V correspond to logic gates (including copy gares). while edges